Samsung patents stacked chips with narrow middle contacts
Samsung describes a design for semiconductor chips where two transistors are stacked vertically. The invention focuses on a specific shape for the metal connection, or contact plug, that links the lower transistor to the upper one. This connection is narrower in the middle than at its ends to fit the stacked structure.
In the filing’s own words
A semiconductor device includes first and second transistors and a first contact plug. The first transistor includes a first gate structure, first channels and a first source/drain layer. The second transistor is disposed on the first transistor, and includes a second gate structure, second channels and a second source/drain layer. The first contact plug extends through the second source/drain layer and contacts an upper surface of the first source/drain layer. A first width in the second direction of a central portion in the first direction of the first contact plug is smaller than a second with in the second direction of each of opposite end portions in the first direction of the first contact plug.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a first transistor including: a first gate structure extending in a first direction; first channels each extending through the first gate structure in a second direction crossing the first direction, the first channels being spaced apart from each other in a third direction perpendicular to the first and second directions; and a first source/drain layer at a first side in the second direction of the first gate structure; a second transistor on the first transistor, the second transistor including: a second gate structure extending in the first direction; second channels each extending through the second gate structure in the second direction, the second channels being spaced apart from each other in the third direction; and a second source/drain layer at a first side in the second direction of the second gate structure; and a first contact plug extending through the second source/drain layer and contacting an upper surface of the first source/drain layer, wherein a first width in the second direction of a central portion in the first direction of the first contact plug is smaller than a second width in the second direction of each of opposite end portions in the first direction of the first contact plug.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICES
- Publication number
- US20260314043A1
- Application number
- 19635194
- Filed
- Mar 31, 2026
- Published
- Oct 8, 2026
- Inventors
- 4
- Claims
- 19
Classified under
H10D 84/83125 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/502 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 62/151 Electricity & electronicsH10D 64/254 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.