Samsung patents chip design using nanosheets of different widths
Samsung describes a method for building semiconductor devices using thin, sheet-like structures called nanosheets. The design creates gate electrodes that wrap around these nanosheets, with specific sections made narrower than others to control the flow of electricity.
In the filing’s own words
A method for manufacturing a semiconductor device, comprising forming first to fourth patterns on a substrate; forming a field insulating layer on a sidewall of each of the first to fourth patterns on the substrate; forming first to fourth plurality of nanosheets on the first to fourth patterns, respectively; and forming first and second gate electrodes extending in the second direction, the first gate electrodes intersecting the first and third patterns, the second gate electrodes intersecting the second and fourth patterns, the first gate electrodes surrounding the first and third plurality of nanosheets, the second gate electrodes surrounding the second and fourth plurality of nanosheets. A width of the first gate electrode of a portion overlapping the first plurality of nanosheets is smaller than a width of the first gate electrode in the first direction of a portion overlapping the third plurality of nanosheets.
What exactly they claim (claim 1)
1. A method for manufacturing a semiconductor device, comprising: forming first to fourth patterns on a substrate, each of the first to fourth patterns extending in a first direction, the second pattern spaced apart from the first pattern in the first direction, the third pattern spaced apart from the first pattern in a second direction different from the first direction, the fourth pattern spaced apart from the third pattern in the first direction; forming a field insulating layer on a sidewall of each of the first to fourth patterns on the substrate; forming a first plurality of nanosheets on the first pattern, a second plurality of nanosheets on the second pattern, a third plurality of nanosheets on the third pattern, and a fourth plurality of nanosheets on the fourth pattern; and forming first and second gate electrodes extending in the second direction, the first gate electrodes intersecting each of the first and third patterns, the second gate electrodes intersecting each of the second and fourth patterns, the first gate electrodes surrounding each of the first and third plurality of nanosheets, the second gate electrodes surrounding each of the second and fourth plurality of nanosheets, wherein a width of the first gate electrode in the first direction of a portion overlapping the first plurality of nanosheets in the first direction is smaller than a width of the first gate electrode in the first direction of a portion overlapping the third plurality of nanosheets in the first direction.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260313982A1
- Application number
- 19709633
- Filed
- Jun 16, 2026
- Published
- Oct 8, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10D 62/121 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6757 Electricity & electronicsH10D 64/021 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.