Samsung patents memory chip design with layered conductive walls
Samsung describes a semiconductor structure for memory chips that uses specific conductive layers on the sides of vertical storage cells. The design places a first conductive layer on one side of the cell and a second layer on the opposite side, wrapping around the first layer to form a complete circuit path. This arrangement is intended to improve how electrical signals are routed within the dense storage area of the chip.
In the filing’s own words
A semiconductor device includes a peripheral circuit area, and a cell array area arranged on the peripheral circuit area, wherein the cell array area includes bit lines extending in a first horizontal direction, active patterns extending in a vertical direction on the bit lines and each including a first side wall and a second side wall opposite to the first side wall, and a word line extending in a second horizontal direction on the bit lines, and including a first conductive layer arranged on the first side wall of each of the active patterns and extending in the second horizontal direction, and a second conductive layer including a first portion arranged on the second side wall of each of the active patterns and including a second portion arranged on a side wall of the first conductive layer, and cell capacitors respectively arranged on the active patterns.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a peripheral circuit area; and a cell array area arranged on the peripheral circuit area, wherein the cell array area comprises: a plurality of bit lines extending in a first horizontal direction; a plurality of active patterns extending in a vertical direction on the plurality of bit lines and each comprising a first side wall and a second side wall opposite to the first side wall; a word line extending in a second horizontal direction crossing the first horizontal direction on the plurality of bit lines, and comprising: a first conductive layer arranged on the first side wall of each of the plurality of active patterns and extending in the second horizontal direction, and a second conductive layer comprising a first portion arranged on the second side wall of each of the plurality of active patterns and comprising a second portion arranged on a side wall of the first conductive layer; and a plurality of cell capacitors arranged on the plurality of active patterns.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE LAYERS AND CELL CAPACITOR
- Publication number
- US20260313961A1
- Application number
- 19640269
- Filed
- Apr 6, 2026
- Published
- Oct 8, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10D 30/6728 Electricity & electronicsH10B 12/315 Electricity & electronicsH10B 12/482 Electricity & electronicsH10B 12/488 Electricity & electronicsH10D 30/6706 Electricity & electronicsH10D 30/6735 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.