Samsung patents chip design using crystalline metal oxide spacers
Samsung describes a method for building a semiconductor device where a crystalline metal oxide material is used as an inner spacer between the gate electrode and the source/drain regions. The process involves growing this oxide layer epitaxially within specific indentations created in a stacked structure before forming the final source/drain patterns.
In the filing’s own words
A semiconductor device includes; a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of spaced apart and vertically stacked semiconductor patterns, a source/drain pattern connected to the plurality of semiconductor patterns, a gate electrode on the plurality of semiconductor patterns, the gate electrode including a portion interposed between adjacent ones of the plurality of semiconductor patterns, and an inner spacer interposed between the portion of the gate electrode and the source/drain pattern, wherein the inner spacer is crystalline metal oxide is expressed by a formula (MO), wherein (O) is an oxygen atom, and (M) is a metal atom selected from a group consisting of Mg, Be, and Ga.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor device, the method comprising: forming a stacked pattern on a substrate, the stacked pattern including alternately stacked active layers and sacrificial layers; forming a sacrificial pattern extending in a first direction on the stacked pattern; etching the stacked pattern using the sacrificial pattern as a mask to form a recess in the stacked pattern, wherein the active layers including a plurality of semiconductor patterns are exposed by the recess; performing a selective etching process on the sacrificial layers exposed by the recess to form indent regions; forming an epitaxial dielectric layer filling the indent regions using the exposed sacrificial layers as seeds, the epitaxial dielectric layer including crystalline metal oxide; wet etching the epitaxial dielectric layer to form respective inner spacers in the indent regions; performing a selective epitaxial growth process using the plurality of semiconductor patterns and the inner spacers as exposed by the recess as seeds to form a source/drain pattern filling the recess; removing the sacrificial pattern and the sacrificial layers to expose the plurality of semiconductor patterns; and sequentially forming a gate insulating layer and a gate electrode on the exposed plurality of semiconductor patterns.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
- Publication number
- US20260313941A1
- Application number
- 19710895
- Filed
- Jun 17, 2026
- Published
- Oct 8, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 64/258 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.