Samsung patents stacked memory design to fit more data in less space
Samsung describes a 3D memory structure where vertical channels are stacked on top of each other with a word line sandwiched between them. This arrangement allows data storage layers to be placed on both the top and bottom of the central word line, maximizing the use of vertical space. The design connects these stacked cells to vertical bit and source lines that run through the structure.
In the filing’s own words
A semiconductor memory device includes a first channel pattern and a second channel pattern stacked on a substrate, a word line disposed between the first and second channel patterns and that extends in a first direction parallel to a top surface of the substrate, a data storage pattern disposed between a top surface of the word line and the first channel pattern and between a bottom surface of the word line and the second channel pattern, a bit line that extends in a second direction perpendicular to the top surface of the substrate and that is connected to first end portions of the first and second channel patterns, and a source line that extends in the second direction and is connected to second end portions of the first and second channel patterns.
What exactly they claim (claim 1)
1. A semiconductor memory device, comprising: a substrate; memory cells stacked in a first direction perpendicular to a top surface of the substrate; word lines stacked in the first direction and extending along a second direction parallel to the top surface of the substrate, the word lines connected to the memory cells, respectively; a bit line extending along the first direction, the bit line connected to first terminals of the memory cells; and a source line extending along the first direction, the source line connected to second terminals of the memory cells, wherein each of the memory cells comprises: a first channel pattern; a second channel pattern on the first channel pattern; and a data storage pattern between the first channel pattern and the second channel pattern.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR MEMORY DEVICE
- Publication number
- US20260313907A1
- Application number
- 19709173
- Filed
- Jun 16, 2026
- Published
- Oct 8, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10B 51/30 Electricity & electronicsH10B 51/20 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.