Samsung patents 3D memory chip using ferroelectric film
Samsung describes a vertical memory structure where two layers of storage cells are stacked on top of each other. The design uses a thin film of ferroelectric material, which holds an electric charge, as an insulating layer between the upper and lower cell layers.
In the filing’s own words
A semiconductor device includes a first bit line extending in a first direction, a first channel pattern on the first bit line, and connected to the first bit line, a first word line on the first channel pattern, and extending in a second direction, a lower gate insulating pattern between the first channel pattern and the first word line, a second bit line extending in the second direction, and spaced apart from the first word line in a third direction, a second channel pattern on the second bit line, and contacting the second bit line, an upper gate insulating pattern between the first channel pattern and the second channel pattern, between the first channel pattern and the second bit line, contacting the first channel pattern, and including a ferroelectric material film, and a second word line on the second channel pattern, and extending in the first direction.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a first bit line extending in a first direction, and comprising a first side and a second side opposite to the first side; a first channel pattern on the first side of the first bit line, and connected to the first bit line; a first word line on the first channel pattern, and extending in a second direction; a lower gate insulating pattern between the first channel pattern and the first word line; a second bit line extending in the second direction, and spaced apart from the first word line in a third direction; a second channel pattern on the second bit line, and in contact with the second bit line; an upper gate insulating pattern between the first channel pattern and the second channel pattern, between the first channel pattern and the second bit line, and in contact with the first channel pattern, the upper gate insulating pattern comprising a ferroelectric material film; and a second word line on the second channel pattern, and extending in the first direction.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC MATERIAL FILM AND METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
- Publication number
- US20260313906A1
- Application number
- 19424974
- Filed
- Dec 18, 2025
- Published
- Oct 8, 2026
- Inventors
- 1
- Claims
- 20
Classified under
H10B 51/30 Electricity & electronicsG11C 5/063 Physics & computingH10B 12/00 Electricity & electronicsH10B 51/20 Electricity & electronicsH10D 30/701 Electricity & electronicsH10D 62/292 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.