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Samsung patents 3D memory design with oxygen-rich layers for better reliability

Patent drawing
Patent drawing from the official filing.

Samsung describes a method for building 3D memory chips by stacking layers of insulating material and gates. The process creates a specific structure where one part of the charge storage layer has a higher oxygen concentration than another, which the filing says improves the device's reliability.

Why it mattersThis is a routine improvement to the manufacturing process of standard computer memory, aiming to make the chips more stable over time.

In the filing’s own words

There is provided a semiconductor memory device having improved reliability. The semiconductor memory device includes a cell substrate, a mold stack including mold insulating layers and gate electrodes, which are alternately stacked on the cell substrate, a semiconductor layer extended in a vertical direction crossing an upper surface of the cell substrate to pass through the mold stack, a blocking insulating pattern between the semiconductor layer and each of the gate electrodes, a charge storage layer including a charge trap portion between the semiconductor layer and the blocking insulating pattern and a first charge blocking portion between the semiconductor layer and each of the mold insulating layers, and a tunnel insulating layer between the semiconductor layer and the charge storage layer, wherein an oxygen concentration of the first charge blocking portion is higher than that of the charge trap portion.

What exactly they claim (claim 1)

1. A method for manufacturing a semiconductor memory device, the method comprising: forming a preliminary mold on a cell substrate, the preliminary mold including mold insulating layers and mold sacrificial layers alternately stacked; forming a channel hole penetrating the preliminary mold in a vertical direction crossing an upper surface of the cell substrate; forming a recess by performing a first recess process on the mold insulating layers exposed by the channel hole to cause a portion of the mold sacrificial layers to protrude toward the channel hole; forming a blocking insulating pattern by performing a first oxidation process on at least the portion of the mold sacrificial layers protruding toward the channel hole; forming a charge storage layer in the channel hole, the charge storage layer including a first charge blocking portion extending along a side surface of each of the mold insulating layers and a charge trap portion extending along a side surface of the blocking insulating pattern; forming a tunnel insulating layer and a semiconductor layer on the charge storage layer in the channel hole sequentially; and forming a mold stack including the mold insulating layers and gate electrodes by replacing the mold sacrificial layers with the gate electrodes, wherein an oxygen concentration of the first charge blocking portion is higher than an oxygen concentration of the charge trap portion.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
SEMICONDUCTOR MEMORY DEVICE, METHOD FOR FABRICATING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME
Publication number
US20260313902A1
Application number
19709263
Filed
Jun 16, 2026
Published
Oct 8, 2026
Inventors
6
Claims
20

Classified under

H10B 43/35 Electricity & electronicsH10B 43/10 Electricity & electronicsH10B 43/27 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.