Samsung patents 3D memory design with tapered channels for better contact
Samsung has filed a patent application for a semiconductor device where channel structures and gate contacts are stacked vertically. The design specifies that the upper parts of these structures are as wide or wider than the lower parts to ensure reliable electrical connections. This layout helps organize the internal wiring of high-density memory chips.
In the filing’s own words
A semiconductor device includes gate electrodes stacked and spaced apart from each other in a first direction; interlayer insulating layers alternately stacked with the gate electrodes; channel structures extending into the gate electrodes in the first direction and each including a channel layer; gate contact plugs extending into the gate electrodes in the first direction and electrically connected to the gate electrodes; common source layers in contact with the channel layers on the channel structures; cell region insulating layers below the channel structures and the gate contact plugs; and bitlines electrically connected to the channel structures in the cell region insulating layer. Lower ends of the channel structures and lower ends of the gate contact plugs are in an insulating structure including a lowermost interlayer insulating layer and the cell region insulating layer.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a first semiconductor structure including a substrate, circuit elements on the substrate, a first interconnection structure on the circuit elements, and first bonding pads on the first interconnection structure; and a second semiconductor structure on the first semiconductor structure, wherein the second semiconductor structure includes gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate; interlayer insulating layers alternately stacked with the gate electrodes; channel structures extending into the gate electrodes in the first direction, wherein each of the channel structures includes a channel layer; gate contact plugs extending into the gate electrodes in the first direction and electrically connected to respective ones of the gate electrodes; common source layers covering upper ends of the channel structures and in contact with the channel layers; second interconnection structures including bitlines electrically connected to respective ones of the channel structures below lower ends of the channel structures; and second bonding pads below the second interconnection structures and connected to the first bonding pads, wherein each of the channel structures includes a plurality of channel portions stacked in the first direction, wherein each of the gate contact plugs includes a plurality of contact portions stacked in the first direction, wherein, in at least one of the plurality of channel portions, a width of an upper surface is a same as or greater than a width of a lower surface, and wherein, in at least one of the plurality of contact portions, a width of an upper surface is a same as or greater than a width of a lower surface.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE WITH ALIGNED CHANNEL STRUCTURES AND GATE CONTACT STRUCTURES
- Publication number
- US20260313896A1
- Application number
- 19562434
- Filed
- Mar 10, 2026
- Published
- Oct 8, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10B 43/27 Electricity & electronicsG11C 5/063 Physics & computingH10B 41/10 Electricity & electronicsH10B 41/27 Electricity & electronicsH10B 41/35 Electricity & electronicsH10B 43/10 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.