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Samsung patents chip design with vertical wires through mold layers

Patent drawing
Patent drawing from the official filing.

Samsung has filed a patent for a semiconductor structure that uses vertical wires, called through electrodes, to connect components within a chip. These wires pass through specific insulating layers and dummy blocks to link different parts of the memory cell structure.

Why it mattersThis is a routine improvement in chip manufacturing that helps engineers connect internal components more efficiently within a semiconductor device.

In the filing’s own words

A semiconductor device including: a cell structure including: a first surface; a second surface opposite to the first surface; and a main block and a dummy block each comprising a cell region and a connection region, in which the dummy block includes: a mold structure comprising at least one gate electrode and at least one mold insulating layer in a first direction in the cell region and the connection region; a common source layer on the mold structure; a first insulating layer on the mold structure and the common source layer; a channel structure connected to the common source layer; a cell plug in contact with the at least one gate electrode; a contact structure passing through the first insulating layer; and a through electrode connected to the contact structure by passing through the mold structure in the first direction in the cell region.

What exactly they claim (claim 1)

1. A semiconductor device comprising: a cell structure comprising: a first surface; a second surface opposite to the first surface; and a main block and a dummy block each comprising a cell region and a connection region, wherein the dummy block comprises: a mold structure comprising at least one gate electrode and at least one mold insulating layer in a first direction in the cell region and the connection region; a common source layer on the mold structure; a first insulating layer on the mold structure and the common source layer; a channel structure connected to the common source layer by passing through the mold structure in the first direction in the cell region; a cell plug in contact with the at least one gate electrode by passing through the mold structure in the first direction in the connection region; a contact structure passing through the first insulating layer; and a through electrode connected to the contact structure by passing through the mold structure in the first direction in the cell region.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
SEMICONDUCTOR DEVICE WITH THROUGH ELECTRODE THROUGH MOLD STRUCTURE
Publication number
US20260313894A1
Application number
19456629
Filed
Jan 22, 2026
Published
Oct 8, 2026
Inventors
4
Claims
20

Classified under

H10B 43/27 Electricity & electronicsH10B 41/10 Electricity & electronicsH10B 41/27 Electricity & electronicsH10B 41/41 Electricity & electronicsH10B 43/10 Electricity & electronicsH10B 43/40 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.