Samsung patents memory layout with mixed bitline structures
Samsung describes a semiconductor design where global bitlines sit above local bitlines in a memory chip. The design uses different structural patterns, called 1-1 and 2-1 bitline structures, for complementary lines to manage data flow.
In the filing’s own words
A semiconductor device includes local bitlines connected to memory cells, global bitlines disposed at a level higher than a level of the local bitlines and extending in a first horizontal direction, and bitline sense amplifiers connected to the global bitlines. The global bitlines include a first global bitline and a first global complementary bitline, complementary to the first global bitline. The first global bitline includes a 1-1 bitline structure, and the first global complementary bitline includes a2-1 bitline structure at least partially overlapping the 1-1 bitline structure in the first horizontal direction. The 1-1 bitline structure includes 1-1 lower lines spaced apart from the 1-1 lower lines in the first horizontal direction and a 1-1 upper line disposed on the 1-1 lower lines and connected to the 1-1 lower lines.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: memory cells arranged in a vertical direction, a first horizontal direction and a second horizontal direction intersecting one another; local bitlines connected to the memory cells and disposed at the same level; and global bitlines disposed at a level higher than the level of the local bitlines and connected to the local bitlines, wherein the global bitlines extend in the first horizontal direction, wherein each of the memory cells includes a cell transistor including a cell gate electrode extending in the second horizontal direction, and a data storage structure, wherein the global bitlines include a first global bitline and a first global complementary bitline, complementary to the first global bitline, wherein the first global bitline includes a 1-1 bitline structure, wherein the first global complementary bitline includes a 2-1 bitline structure at least partially overlapping the 1-1 bitline structure in the first horizontal direction, and wherein the 1-1 bitline structure includes 1-1 lower lines spaced apart from each other in the first horizontal direction and a 1-1 upper line disposed on the 1-1 lower lines and connected to the 1-1 lower lines.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICES INCLUDING GLOBAL BITLINES
- Publication number
- US20260313881A1
- Application number
- 19635210
- Filed
- Mar 31, 2026
- Published
- Oct 8, 2026
- Inventors
- 7
- Claims
- 20
Classified under
H10B 12/482 Electricity & electronicsG11C 11/4091 Physics & computingH10B 12/50 Electricity & electronicsH10B 80/00 Electricity & electronicsH10W 80/312 Electricity & electronicsH10W 90/26 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.