Samsung patents memory chip design with interlocking bit line masks
Samsung describes a method for making semiconductor memory chips by using a specific mask pattern to create bit lines. The design features small protrusions on the mask that extend toward each other, helping to define the spacing between adjacent bit lines during manufacturing.
In the filing’s own words
An example method for manufacturing a semiconductor memory device includes forming a PMOS region, a first NMOS region, and a second NMOS region. Forming the first NMOS region includes forming a first bit line and a second bit line extending in the first direction and spaced apart from each other in a second direction intersecting the first direction. The first mask pattern includes a first bit line mask pattern corresponding to the first bit line and a second bit line mask pattern corresponding to the second bit line, the first bit line mask pattern includes a first protrusion pattern protruding from a first end portion toward the second bit line mask pattern, and the second bit line mask pattern includes a second protrusion pattern protruding from a second end portion toward the first bit line mask pattern.
What exactly they claim (claim 1)
1. A method for manufacturing a semiconductor memory device, the method comprising forming a PMOS region, a first NMOS region, and a second NMOS region on a substrate, wherein the first NMOS region and the second NMOS region are spaced apart from each other in a first direction, and the PMOS region is between the first NMOS region and the second NMOS region, wherein forming the first NMOS region includes: performing a first patterning process to form a first bit line and a second bit line using a first mask pattern, wherein the first bit line and the second bit line extend in the first direction on the substrate and are spaced apart from each other in a second direction intersecting the first direction; and forming a first source pattern between the first bit line and the second bit line, wherein the first mask pattern includes a first bit line mask pattern corresponding to the first bit line and a second bit line mask pattern corresponding to the second bit line, wherein the first bit line mask pattern includes a first protrusion pattern protruding from a first end portion of the first bit line mask pattern toward the second bit line mask pattern, and wherein the second bit line mask pattern includes a second protrusion pattern protruding from a second end portion of the second bit line mask pattern toward the first bit line mask pattern.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE INCLUDING A BIT LINE MASK PATTERN
- Publication number
- US20260313871A1
- Application number
- 19529567
- Filed
- Feb 4, 2026
- Published
- Oct 8, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10B 12/02 Electricity & electronicsG11C 5/063 Physics & computingG11C 11/4091 Physics & computingH10B 12/482 Electricity & electronicsH10B 12/50 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.