Samsung patents 3D chip contact design for better signal flow

1. A semiconductor device, comprising: a first active pattern protruding above a substrate, an upper portion of the first active pattern including a first channel region and a first source/drain region connected to the first channel region; a device isolation pattern on a sidewall of a lower portion of the first active pattern; a first gate electrode on the first channel region of the first active pattern; a first lower conductive structure electrically connected to the first source/drain region; a first conductive structure on the first lower conductive structure, the first conductive structure including a first portion and a second portion that are connected to each other to constitute a single body, the second portion extending from the first portion toward the first lower conductive structure and connected to the first lower conductive structure; an interconnection line on the first conductive structure; a barrier pattern; and a via between the interconnection line and the first portion, and connecting the interconnection line and the first conductive structure, wherein the first conductive structure further includes a third portion extending from the first portion toward the first gate electrode and connected to the first gate electrode, wherein a gap is formed between the third portion and the second portion, the gap being adjacent to the first portion and filled with an insulating layer that contacts a surface of the first portion, wherein the first conductive structure further includes a vertically-extended portion protruding from a bottom of the second portion and covering an upper sidewall of the first lower conductive structure, wherein the vertically-extended portion is spaced apart from the first gate electrode, wherein the barrier pattern comprises a first barrier portion between the second portion of the first conductive structure and the first lower conductive structure, a second barrier portion between the first gate electrode and the third portion of the first conductive structure, and a third barrier portion disposed on a sidewall of the vertically-extended portion of the first conductive structure, wherein the first barrier portion, the second barrier portion, and the third barrier portion of the barrier pattern are formed conformally and configured to cover the first portion, the second portion, the third portion, and the vertically-extended portion of the first conductive structure, and wherein a bottom surface of the vertically-extended portion of the first conductive structure is higher than a bottom surface of the third portion.