Samsung patents memory chip tweak to cut power drain
Samsung describes a memory device that uses a power switch circuit to manage the electrical state of transistors inside a bit line sense amplifier. The circuit adjusts the body voltage of these transistors after they finish reading data to reduce leakage current, then resets them during the precharge phase.
In the filing’s own words
A memory device that includes a bit line sense amplifier including a plurality of NMOS transistors and a plurality of PMOS transistors; and a power switch circuit that reduces a leakage current in the bit line sense amplifier by dynamically controlling one of a body voltage of the plurality of NMOS transistors and a body voltage of the plurality of PMOS transistors. The power switch circuit changes one of the body voltage of the plurality of NMOS transistors and the body voltage of the plurality of PMOS transistors from a first voltage to a second voltage, after the bit line sense amplifier performs an active operation; and changes the one of the body voltage of the plurality of NMOS transistors and the body voltage of the plurality of PMOS transistors from the second voltage to the first voltage, while the bit line sense amplifier performs a precharge operation.
What exactly they claim (claim 1)
1. A memory device comprising: a bit line sense amplifier comprising a plurality of NMOS transistors and a plurality of PMOS transistors; and a power switch circuit configured to reduce a leakage current in the bit line sense amplifier by dynamically controlling one of a body voltage of the plurality of NMOS transistors and a body voltage of the plurality of PMOS transistors, wherein the power switch circuit is configured to change one of the body voltage of the plurality of NMOS transistors and the body voltage of the plurality of PMOS transistors from a first voltage to a second voltage, after the bit line sense amplifier performs an active operation, and change the one of the body voltage of the plurality of NMOS transistors and the body voltage of the plurality of PMOS transistors from the second voltage to the first voltage, while the bit line sense amplifier performs a precharge operation.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- MEMORY DEVICE INCLUDING BIT LINE SENSE AMPLIFIER AND OPERATING METHOD THEREOF
- Publication number
- US20260311744A1
- Application number
- 19419752
- Filed
- Dec 15, 2025
- Published
- Oct 8, 2026
- Inventors
- 4
- Claims
- 20
Classified under
G11C 11/4091 Physics & computingG11C 11/4074 Physics & computingG11C 11/4076 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.