Samsung patents memory layout with shared signal boosters
Samsung describes a memory chip design that splits the storage area into two sections, each with its own signal booster. These sections feed into a shared line that uses a common booster to strengthen the data before it moves to the main output lines.
In the filing’s own words
A memory device includes a cell array having first and second sub cell arrays, and first and second bit line sense amplifiers connected, respectively, to the first and second sub cell arrays. The memory device also includes first and second local I/O line pairs electrically connected, respectively, to a first bit line pair connected to the first bit line sense amplifier and a second bit line pair connected to the second bit line sense amplifier. The memory device further includes a common local I/O line pair connected to the first and second local I/O line pairs, a common local sense amplifier configured to amplify a voltage level transferred from the common local I/O line pair, a global I/O line pair connected to the common local sense amplifier, and an I/O sense amplifier electrically connected to the global I/O line pair.
What exactly they claim (claim 1)
1. A memory device, comprising: a cell array including a first sub cell array and a second sub cell array; a first bit line sense amplifier connected to the first sub cell array; a second bit line sense amplifier connected to the second sub cell array; a first local input/output (I/O) line pair electrically connected to a first bit line pair connected to the first bit line sense amplifier; a second local I/O line pair electrically connected to a second bit line pair connected to the second bit line sense amplifier; a common local I/O line pair connected to the first local I/O line pair and the second local I/O line pair; a common local sense amplifier configured to amplify a voltage level transferred from the common local I/O line pair; a global I/O line pair connected to the common local sense amplifier; and an I/O sense amplifier electrically connected to the global I/O line pair.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- PERIPHERAL CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
- Publication number
- US20260311743A1
- Application number
- 19400447
- Filed
- Nov 25, 2025
- Published
- Oct 8, 2026
- Inventors
- 4
- Claims
- 20
Classified under
G11C 11/4091 Physics & computingG11C 11/4094 Physics & computingG11C 11/4096 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.