Microsoft patents AI method to cut power use in chip designs
Microsoft describes a method that uses a graph neural network to analyze how data changes in a chip's memory cells. It then uses reinforcement learning to create logic that stops the clock signal to cells that are not changing, saving energy.
In the filing’s own words
The disclosed techniques provide a method for reducing power consumption in a logic circuit. A design of the logic circuit is provided. The logic circuit includes storage circuits that store state information and receive clock signals. Toggle activity data indicating whether the stored state information changes in response to a respective clock signal is determined. A graph that represents the toggle activity data is constructed. The graph includes nodes and edges. The nodes correspond to the storage circuits. The edges represent statistical relationships among the determined changes in the stored state information. A graph neural network to the graph is applied. The application includes generating an embedding that characterizes patterns in the toggle activity data. Via a reinforcement learning agent, control logic that selectively gates the clock signals provided to storage circuits for which the stored state information is predicted, based on the embedding, to remain unchanged is determined.
What exactly they claim (claim 1)
1. A method for reducing power consumption in a logic circuit, the method comprising: providing a design of the logic circuit, the logic circuit comprising a plurality of storage circuits configured to store state information and to receive one or more clock signals; determining toggle activity data indicating, for individual storage circuits of the plurality of storage circuits, whether the stored state information changes in response to a respective clock signal; constructing a graph that represents the toggle activity data, the graph comprising nodes and edges, the nodes corresponding to the plurality of storage circuits, and the edges representing statistical relationships among the determined changes in the stored state information; applying a graph neural network to the graph, the application comprising generating an embedding that characterizes patterns in the toggle activity data; via a reinforcement learning (RL) agent executing on a circuit design processing system, determining control logic that selectively gates the one or more clock signals provided to storage circuits for which the stored state information is predicted, based on the embedding, to remain unchanged; and generating an updated version of the design that comprises the determined control logic.
Facts
- Company
- Microsoft (MICROSOFT TECHNOLOGY LICENSING, LLC)
- Official title
- REDUCING POWER CONSUMPTION IN A LOGIC CIRCUIT AND RELATED METHODS
- Publication number
- US20260310875A1
- Application number
- 19253572
- Filed
- Jun 27, 2025
- Published
- Oct 8, 2026
- Inventors
- 3
- Claims
- 20
Classified under
G06F 30/398 Physics & computingG06F 30/27 Physics & computingMore from Microsoft in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.