Microsoft patents method to group memory cells to save chip power
The filing describes a design method that groups small memory components in a chip into different sets to control their power usage. It compares two different grouping strategies to determine which arrangement saves the most energy.
In the filing’s own words
An exemplary method of inserting clock gate circuits in a logic circuit design includes grouping storage circuits in the logic circuit design into a first plurality of groups and also grouping the storage circuits into a second plurality of groups, where the second plurality of groups has fewer groups than the first plurality of groups. The method includes inserting clock gate circuits into the logic circuit design based on the first plurality of groups to generate a first updated circuit design and based on the second plurality of groups to generate a second updated circuit design. The method also includes selecting one of the first updated circuit design and the second updated circuit design based on a comparison of test results of the first updated circuit design and the second updated circuit design. The storage circuits may be grouped based on storage circuits that toggle in a sequence.
What exactly they claim (claim 1)
1. A method of reducing power consumption in a logic circuit, comprising: grouping storage circuits of a logic circuit design into a first plurality of groups; inserting first clock gate circuits into the logic circuit design to generate a first updated circuit design, wherein each first clock gate circuit is configured to selectively couple a clock signal to the storage circuits in a corresponding group of the first plurality of groups; grouping the storage circuits into a second plurality of groups, wherein the second plurality of groups comprises fewer groups than the first plurality of groups; inserting second clock gate circuits into the logic circuit design to generate a second updated circuit design, wherein each second clock gate circuit is configured to selectively couple the clock signal to the storage circuits in a corresponding group of the second plurality of groups; and selecting one of the first updated circuit design and the second updated circuit design as a selected design based on a comparison of a first result of a first test executed on the first updated circuit design and a second result of the first test executed on the second updated circuit design.
Facts
- Company
- Microsoft (Microsoft Technology Licensing, LLC)
- Official title
- REDUCING POWER CONSUMPTION IN A LOGIC CIRCUIT AND RELATED METHODS
- Publication number
- US20260310874A1
- Application number
- 19172605
- Filed
- Apr 7, 2025
- Published
- Oct 8, 2026
- Inventors
- 3
- Claims
- 20
Classified under
G06F 30/398 Physics & computingMore from Microsoft in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.