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Microsoft patents chip design that handles sparse data faster

Patent drawing
Patent drawing from the official filing.

Microsoft has filed a patent for a specialized circuit called a multiply-accumulator (MAC) array, which performs basic math operations like multiplication and addition. The design allows different parts of the circuit to independently pull data from memory based on the type of calculation needed, specifically optimizing for "sparsity" where many data points are zero.

Why it mattersThis is interesting to tech enthusiasts because it describes a hardware method to process data more efficiently, which could lead to faster and more power-efficient processors for future devices.

In the filing’s own words

Embodiments of the present disclosure include a multipurpose multiply-accumulator (MAC) array circuit comprising one or more input memories for receiving operands and a plurality of multiply-accumulator circuits each selectively coupled to the one or more input memories to receive at least a pair of operands and generate a result. Each of the plurality of multiply-accumulator circuits receives operands from the one or more input memories independently. Additionally, selection of operands from the one or more input memories is controlled based on at least an operation and/or data types, where different operation and/or data types configure the plurality of multiply-accumulator circuits to receive different pairs of operands from the one or more input memories to execute particular operation types.

What exactly they claim (claim 1)

1. A multipurpose multiply-accumulator (MAC) array circuit comprising: one or more input memories for receiving operands; and a plurality of multiply-accumulator circuits each selectively coupled to the one or more input memories to receive at least a pair of operands and generate a result, wherein each of the plurality of multiply-accumulator circuits receives operands from the one or more input memories independently, wherein selection of operands from the one or more input memories is controlled based on at least an operation type, wherein different operation types configure the plurality of multiply-accumulator circuits to receive different pairs of operands from the one or more input memories to execute particular operation types.

Facts

Company
Microsoft (Microsoft Technology Licensing, LLC)
Official title
ARRAY CIRCUIT FOR ACCELERATED SPARSITY PROCESSING
Publication number
US20260310411A1
Application number
19562498
Filed
Mar 10, 2026
Published
Oct 8, 2026
Inventors
2
Claims
20

Classified under

G06F 7/5443 Physics & computingG06F 5/06 Physics & computing
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.