Samsung patents memory chip that fixes timing errors in data signals
Samsung describes a memory device with a built-in circuit that adjusts the timing of clock signals to ensure data is sent correctly. It uses reference data to detect and correct small phase shifts before the memory outputs information.
In the filing’s own words
A memory device includes a clock signal correction circuit, a memory system, and an operating method of the memory device. The memory device may include a first correction circuit configured to adjust phases of first to fourth clock signals and output first to fourth corrected clock signals, a second correction circuit configured to output first to fourth offset clock signals based on a size of each of first to fourth reference data included in a first data signal, and a driver configured to output a second data signal based on the first to fourth corrected clock signals.
What exactly they claim (claim 1)
1. A memory device comprising: a memory cell array storing a plurality of data; a first correction circuit configured to receive a plurality of clock signals and a control signal, adjust phases of the plurality of clock signals based on the control signal, and output a plurality of corrected clock signals; a second correction circuit configured to receive the plurality of clock signals through the first correction circuit, adjust the phases of the plurality of clock signals based on a difference between an interval of a first reference data of a plurality of reference data included in a first data signal and a reference unit interval, and output a plurality of offset clock signals, the plurality of reference data being associated with the plurality of clock signals; a control circuit configured to generate the control signal based on the plurality of offset clock signals received from the second correction circuit; and a driver configured to output, based on the plurality of corrected clock signals received from the first correction circuit, a second data signal including the plurality of data read from the memory cell array.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- MEMORY DEVICE INCLUDING CLOCK SIGNAL CORRECTION CIRCUIT, MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY DEVICE
- Publication number
- US20260310358A1
- Application number
- 19696901
- Filed
- Jun 3, 2026
- Published
- Oct 8, 2026
- Inventors
- 2
- Claims
- 20
Classified under
G06F 3/0619 Physics & computingG06F 1/08 Physics & computingG06F 3/0659 Physics & computingG06F 3/0673 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.