Google patents chip sync unit to keep mobile processors in step
Google describes a hardware component for system-on-chip designs that creates a shared timing signal to coordinate different processing units. This unit tracks the status of each component and manages when they should work together during mixed computing tasks.
In the filing’s own words
Methods and systems, including computer-readable media, are described for implementing a hardware synchronization unit at an integrated circuit, such as a system-on-chip (“SoC”) of a mobile device. The synchronization unit is configured to generate a global sync object that is used to control and manage one or more synchronization events at the SoC. The synchronization unit determines context states with reference to the global sync object. Each of the context states correspond to a respective IP device among multiple IP devices on the SoC. The synchronization unit generates register values that represent each of the context states and manages execution of synchronization events based on the global sync object and the register values. The synchronization events involve each IP device and are executed concurrent with a heterogeneous compute performed at the SoC using the IP devices.
What exactly they claim (claim 1)
1. A method performed at a system-on-chip (“SoC”) of a user device using a hardware sync unit of the SoC, the method comprising: generating, by the hardware sync unit, a global sync object that is used to control and manage one or more synchronization events at the SoC; determining, by the hardware sync unit, a plurality of context states with reference to the global sync object, each of the plurality of context states corresponding to a respective IP device of a plurality of IP devices on the SoC; generating, at the hardware sync unit, a plurality of register values that represent each of the plurality of context states corresponding to each respective IP device; and managing, by the hardware sync unit, an execution of synchronization events involving each of the plurality of IP devices based on the global sync object and the plurality of register values.
Facts
- Company
- Google (Google LLC)
- Official title
- Hardware Mechanism for Universal Synchronization of Communications in an SOC
- Publication number
- US20260310254A1
- Application number
- 19483926
- Filed
- May 24, 2023
- Published
- Oct 8, 2026
- Inventors
- 4
- Claims
- 20
Classified under
G06F 1/12 Physics & computingMore from Google in Chips & hardware
- Google patents quantum gates to simulate particle physics Sep 1, 2026
- Waymo patents lidar chips that split light into multiple beams Sep 8, 2026
- Google patents chip design to speed up AI math tasks Sep 8, 2026
- Google patents display that turns off colors to save battery Sep 8, 2026
- Google patents display tech that skips blank screen areas to save power Sep 15, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.
