Samsung patents stacked chip design with specific spacing gaps
Samsung describes a semiconductor package where multiple chips are stacked vertically on top of a base chip. The design uses non-conductive layers to fill gaps between the stacked chips and a mold layer to enclose the structure, with specific distances maintained between different layers.
In the filing’s own words
A semiconductor package includes a first semiconductor chip, a chip stack on the first semiconductor chip, and a mold layer enclosing the chip stack, on the first semiconductor chip. The chip stack includes second semiconductor chips vertically stacked on the first semiconductor chip, a third semiconductor chip on the second semiconductor chips, and non-conductive layers filling spaces between adjacent ones of the second semiconductor chips. The mold layer fills spaces between the first semiconductor chip and the chip stack, which are spaced apart from each other by a first distance, and between the uppermost one of the second semiconductor chips and the third semiconductor chip, which are spaced apart from each other by a second distance. The second semiconductor chips are spaced apart from each other by a third distance that is smaller than the first distance and the second distance.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a first semiconductor chip; a chip stack on the first semiconductor chip; and a mold layer on the chip stack and the first semiconductor chip, wherein the chip stack comprises: second semiconductor chips on the first semiconductor chip; a third semiconductor chip on the second semiconductor chips; and non-conductive layers in spaces between adjacent ones of the second semiconductor chips, wherein the mold layer is in a space between the first semiconductor chip and the chip stack, and the mold layer is in a space between an uppermost one of the second semiconductor chips and the third semiconductor chip, wherein each of the non-conductive layers comprises a protruding portion in a region on a side surface of an adjacent one of the second semiconductor chips, and wherein each protruding portion is spaced apart from one another.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR PACKAGE
- Publication number
- US20260305477A1
- Application number
- 19701055
- Filed
- Jun 8, 2026
- Published
- Oct 1, 2026
- Inventors
- 1
- Claims
- 20
Classified under
H10W 90/00 Electricity & electronicsH10B 80/00 Electricity & electronicsH10W 70/611 Electricity & electronicsH10W 70/635 Electricity & electronicsH10W 74/111 Electricity & electronicsH10W 72/07252 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.