Samsung patents chip stacks linked by wires instead of tiny pillars
Samsung describes a semiconductor package where multiple chips are stacked vertically on a base. Instead of using tiny vertical pillars to connect the layers, the design uses standard bonding wires to link the chips together and connect them to the base.
In the filing’s own words
A semiconductor package includes: a substrate including a first surface and a second surface opposite to each other, and connection pads on the first surface of the substrate; a first chip disposed on the first surface of the substrate; a first chip stack including a plurality of second chips, the plurality of second chips sequentially stacked on the first chip with active surfaces facing downward toward the substrate; a second chip stack including a plurality of third chips, the plurality of third chips sequentially stacked on the first chip with active surfaces facing downward toward the substrate; and an encapsulation layer covering the first chip, the first chip stack and the second chip stack on the first surface of the substrate, wherein the first chip stack and the second chip stack are spaced apart from each other in a first direction parallel to the first surface of the substrate, the plurality of second chips are electrically connected to each other through first bonding wires, the plurality of third chips are electrically connected to each other through second bonding wires, and a set of lowermost first bonding wires of the first bonding wires and a set of lowermost second bonding wires of the second bonding wires are connected to the connection pads, respectively.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a substrate comprising a first surface and a second surface opposite to each other, and connection pads on the first surface of the substrate; a first chip disposed on the first surface of the substrate; a first chip stack comprising a plurality of second chips, the plurality of second chips sequentially stacked on the first chip with active surfaces facing downward toward the substrate; a second chip stack comprising a plurality of third chips, the plurality of third chips sequentially stacked on the first chip with active surfaces facing downward toward the substrate; and an encapsulation layer covering the first chip, the first chip stack and the second chip stack on the first surface of the substrate, wherein the first chip stack and the second chip stack are spaced apart from each other in a first direction parallel to the first surface of the substrate, wherein the plurality of second chips are electrically connected to each other through first bonding wires, and the plurality of third chips are electrically connected to each other through second bonding wires, and a set of lowermost first bonding wires of the first bonding wires and a set of lowermost second bonding wires of the second bonding wires are connected to the connection pads, respectively.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR PACKAGE USING BONDING WIRE AS INTERCONNECTION AND METHOD OF MANUFACTURING THE SAME
- Publication number
- US20260305411A1
- Application number
- 19183982
- Filed
- Apr 21, 2025
- Published
- Oct 1, 2026
- Inventors
- 1
- Claims
- 20
Classified under
H10W 70/65 Electricity & electronicsH10W 74/01 Electricity & electronicsH10W 74/117 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 46/00 Electricity & electronicsH10W 90/24 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.