Samsung patents chip design with extra space around vertical connections
Samsung describes a semiconductor structure that uses a trench to create a gap between a vertical metal connection and the surrounding insulating material. This design includes a spacer to keep the connection isolated, which may help manage heat or stress during manufacturing.
In the filing’s own words
A semiconductor device includes a first interlayer insulating layer, a lower wiring layer disposed in the first interlayer insulating layer, a connection trench formed on an upper surface of the lower wiring layer within the first interlayer insulating layer, the connection trench extending in a vertical direction from the upper surface of the lower wiring layer to an upper surface of the first interlayer insulating layer, an etching stop layer disposed along the upper surface of the first interlayer insulating layer, and sidewalls and a bottom surface of the connection trench, a second interlayer insulating layer disposed on an upper surface of the etching stop layer, a via disposed on the upper surface of the lower wiring layer within the second interlayer insulating layer, at least a portion of the via disposed within the connection trench, the via spaced apart from the sidewalls of the connection trench in a first horizontal direction and in a second horizontal direction perpendicular to the first horizontal direction, and a spacer surrounding sidewalls of the via, and at least a portion of the spacer disposed within the connection trench.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a first interlayer insulating layer; a lower wiring layer disposed in the first interlayer insulating layer; a connection trench formed on an upper surface of the lower wiring layer within the first interlayer insulating layer, the connection trench extending in a vertical direction from the upper surface of the lower wiring layer to an upper surface of the first interlayer insulating layer; an etching stop layer disposed along the upper surface of the first interlayer insulating layer, and sidewalls and a bottom surface of the connection trench; a second interlayer insulating layer disposed on an upper surface of the etching stop layer; a via disposed on the upper surface of the lower wiring layer within the second interlayer insulating layer, at least a portion of the via disposed within the connection trench, the via spaced apart from the sidewalls of the connection trench in a first horizontal direction and in a second horizontal direction perpendicular to the first horizontal direction; and a spacer surrounding sidewalls of the via, and at least a portion of the spacer disposed within the connection trench.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE INCLUDING VIA
- Publication number
- US20260305296A1
- Application number
- 19393384
- Filed
- Nov 18, 2025
- Published
- Oct 1, 2026
- Inventors
- 5
- Claims
- 18
Classified under
H10W 20/42 Electricity & electronicsH10W 20/033 Electricity & electronicsH10W 20/056 Electricity & electronicsH10W 20/074 Electricity & electronicsH10W 20/076 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.