Samsung patents chip design with different insulating layers for P and N transistors
Samsung has filed a patent for a semiconductor device that arranges P-type and N-type transistors side-by-side on a single substrate. The design uses specific insulating structures above the source and drain regions, with the insulator for the P-type section spaced away from the metal contacts while the N-type insulator touches them.
In the filing’s own words
A semiconductor device comprises a substrate including a PMOSFET region and an NMOSFET region, a pair of first channel patterns spaced apart in a first direction on the PMOSFET region, first source/drain patterns at respective sides of the pair of first channel patterns in a second direction crossing the first direction, a first gate pattern surrounding at least a portion of the first channel patterns, a pair of second channel patterns spaced apart in the first direction on the NMOSFET region, second source/drain patterns at respective sides of the pair of second channel patterns in the second direction, a second gate pattern surrounding at least a portion of the second channel patterns, a first upper insulating structure between a pair of the first source/drain patterns, and a second upper insulating structure between a pair of the second source/drain patterns.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a substrate including a PMOSFET region and an NMOSFET region; a pair of first channel patterns spaced apart in a first direction on the PMOSFET region; first source/drain patterns at respective sides of each first channel pattern of the pair of first channel patterns in a second direction crossing the first direction; a first gate pattern surrounding at least a portion of the pair of first channel patterns; a pair of second channel patterns spaced apart in the first direction on the NMOSFET region; second source/drain patterns at respective sides of each second channel pattern of the pair of second channel patterns in the second direction; a second gate pattern surrounding at least a portion of the pair of second channel patterns; a first upper insulating structure between a pair of the first source/drain patterns at a first side of the pair of first channel patterns; and a second upper insulating structure between a pair of the second source/drain patterns at a first side of the pair of second channel patterns, wherein the first upper insulating structure is spaced apart from the first source/drain patterns in the first direction, wherein at least a portion of the second upper insulating structure is in contact with the second source/drain patterns, wherein a bottom level of the first upper insulating structure is higher than bottom levels of the pair of first source/drain patterns, and wherein a bottom level of the second upper insulating structure is higher than bottom levels of the pair of second source/drain patterns.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260304945A1
- Application number
- 19301302
- Filed
- Aug 15, 2025
- Published
- Oct 1, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10D 84/851 Electricity & electronicsH10D 84/0167 Electricity & electronicsH10D 84/017 Electricity & electronicsH10D 84/0188 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.