Samsung patents chip design with tapered edges to improve transistor control
Samsung describes a microchip layout where the control gates of transistors are slightly narrower at their ends than in the middle. This design involves placing insulating material between adjacent gate lines to manage electrical behavior at the edges of the active regions.
In the filing’s own words
An integrated circuit device includes a first fin-type active region and a second fin-type active region extending in a first lateral direction on a substrate, a first gate line extending in a second lateral direction intersecting the first lateral direction on the first fin-type active region, a second gate line apart from the first gate line in the second lateral direction on the second fin-type active region and extending along an extension line of the first gate line in the second lateral direction, and a gate cut insulating pattern between the first gate line and the second gate line, wherein, for at least one of the first gate line and the second gate line, a width of a terminal gate portion, which is adjacent to the gate cut insulating pattern, in the first lateral direction is less than a width of another portion in the first lateral direction.
What exactly they claim (claim 1)
1. An integrated circuit device comprising: a first fin-type active region and a second fin-type active region extending parallel to each other in a first lateral direction on a substrate, the first fin-type active region and the second fin-type active region being apart from each other in a second lateral direction, the second lateral direction intersecting the first lateral direction; a first gate line on the first fin-type active region, the first gate line extending in the second lateral direction; a second gate line on the second fin-type active region, the second gate line being apart from the first gate line in the second lateral direction and extending along an extension line of the first gate line in the second lateral direction; and a gate cut insulating pattern between the first gate line and the second gate line, wherein, for at least one of the first gate line and the second gate line, a width of a terminal gate portion, which is adjacent to the gate cut insulating pattern, in the first lateral direction is less than a width of another portion in the first lateral direction.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- INTEGRATED CIRCUIT DEVICE
- Publication number
- US20260304935A1
- Application number
- 19697000
- Filed
- Jun 3, 2026
- Published
- Oct 1, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10D 84/85 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6757 Electricity & electronicsH10D 62/115 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.