Samsung patents chip design with buried wiring for better connections
Samsung has filed a patent for a semiconductor device that places wiring structures underneath the main chip layers. The design uses a buried insulating pattern and specific contacts to connect the chip's active areas to this lower wiring, potentially improving how electrical signals travel through the device.
In the filing’s own words
A semiconductor device includes a first region and a second region, the semiconductor device including a substrate which includes an insulating pattern in the first region, and a first semiconductor pattern in the second region, a separation pattern separating the insulating pattern and the first semiconductor pattern, between the insulating pattern and the first semiconductor pattern, a first active pattern on the insulating pattern, a first gate structure intersecting the first active pattern, a first source/drain region connected to the first active pattern, on a sidewall of the first gate structure, a second active pattern on the first semiconductor pattern, a second gate structure intersecting the second active pattern, a buried pattern on the first semiconductor pattern, a backside wiring structure on the insulating pattern and on the buried pattern and a back source/drain contact penetrating the insulating pattern, and connects the first source/drain region and the backside wiring structure.
What exactly they claim (claim 1)
1. A semiconductor device which includes a first region and a second region that are different from one another, the semiconductor device comprising: a substrate which includes an insulating pattern in the first region, and a first semiconductor pattern in the second region; a separation pattern which separates the insulating pattern and the first semiconductor pattern, between the insulating pattern and the first semiconductor pattern; a first active pattern on an upper surface of the insulating pattern; a first gate structure which intersects the first active pattern; a first source/drain region which is connected to the first active pattern, on a sidewall of the first gate structure; a second active pattern on an upper surface of the first semiconductor pattern; a second gate structure which intersects the second active pattern; a buried pattern on a lower surface of the first semiconductor pattern; a backside wiring structure on a lower surface of the insulating pattern and on a lower surface of the buried pattern; and a back source/drain contact which penetrates the insulating pattern, and connects the first source/drain region and the backside wiring structure, wherein the buried pattern includes a liner film extending along profiles of the lower surface of the first semiconductor pattern and the sidewall of the separation pattern, and a buried insulating film on the liner film.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE INCLUDING A BURIED PATTERN
- Publication number
- US20260304933A1
- Application number
- 19437024
- Filed
- Dec 30, 2025
- Published
- Oct 1, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10D 84/832 Electricity & electronicsH10D 64/2565 Electricity & electronicsH10D 84/0151 Electricity & electronicsH10D 62/121 Electricity & electronicsH10W 20/43 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.