Samsung patents chip design with variable spacer thicknesses

1. A semiconductor device comprising: a substrate including an active region extending in a first direction; a plurality of gate structures extending on the substrate in a second direction and intersecting the active region, the plurality of gate structures including a first gate structure and a second gate structure spaced apart from each other in the first direction; a plurality of channel layers on the active region and spaced apart from each other in a third direction that is perpendicular to an upper surface of the substrate, wherein the plurality of channel layers comprise first channel layers surrounded by the first gate structure and second channel layers surrounded by the second gate structure; a plurality of source/drain regions in a region in which the active region is recessed, on a first side of each of the plurality of gate structures, wherein the plurality of source/drain regions comprise a first source/drain region connected to the first channel layers, a second source/drain region connected to the first channel layers and the second channel layers, and a third source/drain region connected to the second channel layers; first internal spacer layers between the first gate structure and the first source/drain region, wherein the first internal spacer layers are below each of the first channel layers on the active region; second internal spacer layers between the first gate structure and the second source/drain region, wherein the second internal spacer layers are below each of the first channel layers on the active region; third internal spacer layers between the second gate structure and the second source/drain region, wherein the third internal spacer layers are below each of the second channel layers on the active region; and fourth internal spacer layers between the second gate structure and the third source/drain region, wherein the fourth internal spacer layers are below each of the second channel layers on the active region, wherein a central thickness of each of the second internal spacer layers in the first direction is greater than a central thickness of each of the first internal spacer layers in the first direction, and a central thickness of each of the third internal spacer layers in the first direction is greater than a central thickness of each of the fourth internal spacer layers in the first direction.