Samsung patents semiconductor design with varying germanium layers
Samsung describes a method for building a semiconductor device where two different sections use distinct patterns of silicon and germanium layers. The design involves creating one section with wider channels and fewer layers, while the other has narrower channels and more layers to optimize performance.
In the filing’s own words
A semiconductor device includes first and second active patterns on first and second PMOS regions, two first source/drain patterns spaced apart along a first direction on the first active pattern and a first channel pattern including first semiconductor patterns between the two first source/drain patterns, and two second source/drain patterns spaced apart along the first direction on the second active pattern and a second channel pattern including second semiconductor patterns between the two second source/drain patterns. A width in a second direction of the each of the first semiconductor patterns is greater than a width of each of the second semiconductor patterns. Each of the first and second source/drain patterns includes semiconductor layers having different germanium concentrations. A number of the semiconductor layers of each of the two second source/drain patterns is greater than a number of the semiconductor layers of each of the two first source/drain patterns.
What exactly they claim (claim 1)
1. A method of fabricating a semiconductor device, the method comprising: forming a first pattern and a second pattern respectively on a first PMOS region and a second PMOS region of a substrate, wherein the first pattern has a first width in a first direction parallel to a top surface of the substrate, and wherein the second pattern has a second width in the first direction less than the first width; forming a first stack pattern and a second stack pattern on the first pattern and the second pattern, respectively, wherein each of the first stack pattern and the second stack pattern includes sacrificial layers and active layers that are alternately stacked; forming a first sacrificial pattern and a second sacrificial pattern that extend along the first direction on the first stack pattern and the second stack pattern, respectively; forming first recesses and second recesses using the first sacrificial pattern and the second sacrificial pattern, respectively, wherein the first recesses are on opposite sides of the first sacrificial pattern, and wherein the second recesses are on opposite sides of the second sacrificial pattern; forming a plurality of first semiconductor layers that fill the first recesses; and forming a plurality of second semiconductor layers that fill the second recesses, wherein the plurality of first semiconductor layers and the plurality of second semiconductor layers include germanium whose concentration increases in a direction from an underlying layer toward an overlying layer, and wherein forming the plurality of first semiconductor layers is performed sequentially with forming the plurality of second semiconductor layers.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
- Publication number
- US20260304920A1
- Application number
- 19703370
- Filed
- Jun 10, 2026
- Published
- Oct 1, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10D 84/83 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 62/151 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.