Samsung patents chip design using variable-width gates on tiny fins
Samsung describes a method for making semiconductor chips where the control gates on tiny silicon fins change width at the boundary between two different chip regions. The filing explains how to etch the substrate to create these fins and then place gate structures that span across them, with narrower sections positioned over an isolation area to separate the regions.
In the filing’s own words
A method of manufacturing a semiconductor device includes etching a portion of a substrate to form first active fins extending in a first direction on a first region of the substrate and second active fins extending in the first direction on a second region of the substrate, respectively, forming a first isolation pattern on a boundary region between the first region and the second region, forming a first gate structure on the first active fins, the first gate structure extending in a second direction perpendicular to the first direction while crossing the first active fins, and the first gate structure extending onto an upper surface of the first isolation pattern, forming a second gate structure on the second active fins, the second gate structure extending in the second direction while crossing the second active fins, and the second gate structure extending onto the upper surface of the first isolation pattern.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor device, the method comprising: etching a portion of a substrate to form first active fins extending in a first direction on a first region of the substrate and second active fins extending in the first direction on a second region of the substrate, respectively; forming a first isolation pattern on a boundary region between the first region and the second region of the substrate; forming a first gate structure on the first active fins, the first gate structure extending in a second direction perpendicular to the first direction while crossing the first active fins, and the first gate structure extending onto an upper surface of the first isolation pattern; and forming a second gate structure on the second active fins, the second gate structure extending in the second direction while crossing the second active fins, and the second gate structure extending onto the upper surface of the first isolation pattern, wherein the first gate structure includes a first portion having a first width and a second portion having a second width less than the first width, and the second gate structure includes a third portion having the first width and a fourth portion having the second width, and wherein each of the second portion and the fourth portion are disposed on the first isolation pattern, and the second portion and the fourth portion face each other in the second direction and are spaced apart from each other.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE INCLUDING FIN FIELD-EFFECT TRANSISTORS ON ACTIVE FINS WITH DIFFERENT GATE WIDTH IN BOUNDARY REGION
- Publication number
- US20260304900A1
- Application number
- 19700859
- Filed
- Jun 8, 2026
- Published
- Oct 1, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10D 64/518 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 84/83 Electricity & electronicsH10D 84/834 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.