Samsung patents chip design with insulating layer between active areas
Samsung describes a semiconductor device structure that places a specific insulating layer between two active regions of a chip. This central layer sits within an opening in an intermediate insulating layer, helping to separate the conductive parts of the device.
In the filing’s own words
A semiconductor device may include a substrate; an active pattern extending on the first surface of the substrate in a first direction and including at least one conductivity-type impurity region; a first conductivity-type epitaxial pattern on the at least one conductivity-type impurity region; a second conductivity-type epitaxial pattern on the at least one conductivity-type impurity region, and spaced apart from the first conductivity-type epitaxial pattern in the first direction; a first interlayer insulating layer on the first surface of the substrate and the first and second conductivity epitaxial patterns; a first intermediate insulating layer on the first interlayer insulating layer and including a first opening extending in a second direction, intersecting the first direction; and a central insulating layer between the first and second conductivity-type epitaxial patterns, and extending in the second direction and in the first opening.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a substrate; an active pattern extending in a first direction on a first surface of the substrate, the active pattern comprising at least one conductivity-type impurity region; a first conductivity-type epitaxial pattern on the at least one conductivity-type impurity region; a second conductivity-type epitaxial pattern on the at least one conductivity-type impurity region, and spaced apart from the first conductivity-type epitaxial pattern in the first direction; a first interlayer insulating layer on the first surface of the substrate, the first conductivity-type epitaxial pattern, and the second conductivity-type epitaxial pattern; a first intermediate insulating layer on the first interlayer insulating layer, the first intermediate insulating layer including a first opening extending in a second direction, intersecting the first direction; a central insulating layer between the first conductivity-type epitaxial pattern and the second conductivity-type epitaxial pattern, wherein the central insulating layer extends in the second direction and is in the first opening; and contact structures penetrating through the first interlayer insulating layer and the first intermediate insulating layer, and respectively in contact with the first conductivity-type epitaxial pattern and the second conductivity-type epitaxial pattern.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICES INCLUDING CENTRAL INSULATING LAYER
- Publication number
- US20260304891A1
- Application number
- 19338572
- Filed
- Sep 24, 2025
- Published
- Oct 1, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10D 64/251 Electricity & electronicsH10D 84/832 Electricity & electronicsH10W 20/20 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.