Samsung patents stacked transistor design for smaller chips
Samsung describes a method for building a field-effect transistor, a basic switch in computer chips, by stacking multiple layers of semiconductor material. The filing details a specific manufacturing process that uses temporary layers to carve out precise shapes, allowing the gate electrode to fit tightly around the stacked channels.
In the filing’s own words
A semiconductor device includes: an active pattern disposed on a substrate; a source/drain pattern disposed on the active pattern; a channel pattern connected to the source/drain pattern, wherein the channel pattern includes semiconductor patterns stacked on each other and spaced apart from each other; and a gate electrode disposed on the channel pattern and extending in a first direction, wherein the gate electrode includes: a channel neighboring part adjacent to a first sidewall of a first semiconductor pattern of the stacked semiconductor patterns; and a body part spaced apart from the first semiconductor pattern, wherein the channel neighboring part is disposed between the body part and the first semiconductor pattern, wherein the first sidewall of the first semiconductor pattern has a first width, wherein the channel neighboring part has a second width less than the first width. The body part has a third width greater than the second width.
What exactly they claim (claim 1)
1. A method for manufacturing a semiconductor device, the method comprising: alternately stacking sacrificial layers and active layers on a substrate; forming a stack pattern on an active pattern by patterning the sacrificial layers and the active layers; forming an etch facilitation layer on the stack pattern; forming a sacrificial semiconductor layer on the etch facilitation layer; forming a sacrificial pattern by etching the sacrificial semiconductor layer, wherein the etch facilitation layer is patterned together with the sacrificial semiconductor layer in the etching of the sacrificial semiconductor layer; forming a recess by etching the stack pattern at a side of the sacrificial pattern; forming a source/drain pattern in the recess; forming an outer region by removing the sacrificial pattern and the etch facilitation layer; forming inner regions by removing the sacrificial layers exposed by the outer region; and forming a gate electrode in the outer region and the inner regions, wherein an etch rate of the etch facilitation layer is greater than an etch rate of the sacrificial semiconductor layer in the etching of the sacrificial semiconductor layer.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE INCLUDING A FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME
- Publication number
- US20260304871A1
- Application number
- 19702022
- Filed
- Jun 9, 2026
- Published
- Oct 1, 2026
- Inventors
- 7
- Claims
- 20
Classified under
H10D 62/235 Electricity & electronicsH10D 62/151 Electricity & electronicsH10D 64/021 Electricity & electronicsH10D 84/0128 Electricity & electronicsH10D 84/013 Electricity & electronicsH10D 84/0147 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.