Samsung patents 3D chip layout with overlapping gate and drain
Samsung describes a method for building a semiconductor device where a gate electrode is placed so it overlaps a source/drain electrode on opposite sides of a channel. This specific arrangement is created by etching trenches into insulating layers and filling them with conductive materials.
In the filing’s own words
A semiconductor device includes a substrate. A first channel pattern is disposed on the substrate. The first channel pattern includes a first side and a second side opposite to each other in a first direction. A first gate electrode is disposed on the first side of the first channel pattern. A first source/drain electrode is disposed on the first side of the first channel pattern. A second source/drain electrode is disposed on the second side of the first channel pattern. The first gate electrode overlaps the second source/drain electrode in the first direction.
What exactly they claim (claim 1)
1. A method for fabricating a semiconductor device, comprising: forming a stacked structure in which a sacrificial mold film and a channel film are alternately stacked on a substrate; forming an inner mold insulating film and a first channel pattern including a first side and a second side opposite to each other in a first direction by patterning the stacked structure; forming an outer mold insulating film covering side surfaces of the inner mold insulating film and side surfaces of the first channel pattern on the substrate; forming a first source/drain trench exposing at least a portion of the first side of the first channel pattern and a second source/drain trench exposing at least a portion of the second side of the first channel pattern by removing a portion of the outer mold insulating film; forming a first source/drain electrode inside the first source/drain trench, and forming a second source/drain electrode inside the second source/drain trench; forming a first gate trench exposing at least a portion of the first side of the first channel pattern by removing a portion of the outer mold insulating film; and forming a first gate electrode inside the first gate trench, wherein the first gate electrode overlaps the second source/drain electrode in the first direction.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260304836A1
- Application number
- 19698116
- Filed
- Jun 4, 2026
- Published
- Oct 1, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10D 30/6729 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6757 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 64/258 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.