Samsung patents 3D ferroelectric memory chip manufacturing method
Samsung has filed a patent application describing a step-by-step process for building a three-dimensional ferroelectric memory device. The method involves stacking conductive and insulating layers on a substrate, creating vertical channels, and placing a ferroelectric material on the side of the conductive pattern before adding a gate electrode.
In the filing’s own words
A method of manufacturing a three-dimensional ferroelectric memory device, including forming a conductive pattern and a gate insulation pattern on a substrate, the conductive pattern and the gate insulation pattern being stacked in a horizontal direction substantially parallel to an upper surface of the substrate; forming a first source/drain pattern on the substrate adjacent to the gate insulation pattern; forming a channel on the first source/drain pattern, the channel extending in a vertical direction substantially perpendicular to the upper surface of the substrate, and the gate insulation pattern covering a sidewall of the channel; forming a second source/drain pattern at an upper portion of the channel; forming a ferroelectric pattern on a portion of an outer sidewall of the conductive pattern; and forming a gate electrode on the ferroelectric pattern.
What exactly they claim (claim 1)
1. A method of manufacturing a three-dimensional ferroelectric memory device, the method comprising: forming a conductive pattern and a gate insulation pattern on a substrate, the conductive pattern and the gate insulation pattern being stacked in a horizontal direction substantially parallel to an upper surface of the substrate; forming a first source/drain pattern on the substrate adjacent to the gate insulation pattern; forming a channel on the first source/drain pattern, the channel extending in a vertical direction substantially perpendicular to the upper surface of the substrate, and the gate insulation pattern covering a sidewall of the channel; forming a second source/drain pattern at an upper portion of the channel; forming a ferroelectric pattern on a portion of an outer sidewall of the conductive pattern; and forming a gate electrode on the ferroelectric pattern.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- METHOD OF MANUFACTURING THREE-DIMENSIONAL FERROELECTRIC MEMORY DEVICES
- Publication number
- US20260304779A1
- Application number
- 19704601
- Filed
- Jun 11, 2026
- Published
- Oct 1, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10B 51/20 Electricity & electronicsH10B 51/10 Electricity & electronicsH10D 30/701 Electricity & electronicsH10D 64/689 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.