Samsung patents chip design with stacked wiring layers
Samsung describes a semiconductor device layout where signal wires are placed above circuit wires on a chip. The design uses specific insulating layers and contact plugs to connect these stacked layers while keeping them physically separated.
In the filing’s own words
The present disclosure relates to a semiconductor device, and according to an embodiment, the semiconductor device includes a substrate including a cell array region and a core/periphery region around the cell array region, a circuit wiring on the core/periphery region of the substrate, a signal wiring spaced apart from the circuit wiring in a direction perpendicular to an upper surface of the substrate, a contact plug connecting the circuit wiring and the signal wiring, an etch stop layer surrounding an outer peripheral surface of an upper portion of the contact plug, and a wiring insulating layer covering an upper surface of the contact plug and an upper surface of the etch stop layer and covering a side surface of the signal wiring, wherein a lower surface of the signal wiring is positioned at a higher level than a lower surface of the etch stop layer.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a substrate including a cell array region and a core/periphery region disposed around the cell array region, a circuit wiring disposed on the core/periphery region of the substrate; a signal wiring disposed apart from the circuit wiring in a direction perpendicular to an upper surface of the substrate, a contact plug connecting the circuit wiring and the signal wiring, an etch stop layer surrounding an outer surface of an upper portion of the contact plug, and a wiring insulating layer covering an upper surface of the contact plug and an upper surface of the etch stop layer, and covering a side surface of the signal wiring, wherein a lower surface of the signal wiring is positioned at a higher level than a lower surface of the etch stop layer.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260304757A1
- Application number
- 19381065
- Filed
- Nov 6, 2025
- Published
- Oct 1, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10B 12/50 Electricity & electronicsH10B 12/09 Electricity & electronicsH10B 12/315 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.