Samsung patents chip design with flat contact points for better manufacturing
Samsung describes a semiconductor layout where the metal connections near the edge of the memory area are kept within 5 nanometers of the same height as those further inside. This minimizes the vertical step difference between adjacent contacts to improve the manufacturing process. The filing focuses on the physical structure of the chip's substrate and contact plugs.
In the filing’s own words
A semiconductor device includes a substrate including a cell array region and a core region disposed around the cell array region; a plurality of storage element contacts; a contact plug; and a contact plug spacer. The plurality of storage element contacts may include a first storage element contact and at least one second storage element contact, the first storage element contact is a closest storage element contact of the plurality of storage element contacts to the core region, such that the first storage element contact is between the core region and the at least one second storage element contact. A step difference in a vertical direction perpendicular to the substrate between a top surface of the first storage element contact and a top surface of the at least one second storage element contact is 5 nm or less.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a substrate including a cell array region and a core region; a plurality of storage element contacts in the cell array region; a contact plug in the core region; and a contact plug spacer on a sidewall of the contact plug, wherein, the plurality of storage element contacts includes a first storage element contact and at least one second storage element contact, the first storage element contact is a closest storage element contact of the plurality of storage element contacts to the core region in a direction parallel to the substrate, such that the first storage element contact is between the core region and the at least one second storage element contact, and a step difference in a vertical direction perpendicular to the substrate between a top surface of the first storage element contact and a top surface of the at least one second storage element contact is 5 nm or less.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
- Publication number
- US20260304750A1
- Application number
- 19708238
- Filed
- Jun 15, 2026
- Published
- Oct 1, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10B 12/315 Electricity & electronicsH10B 12/03 Electricity & electronicsH10B 12/482 Electricity & electronicsH10D 64/512 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.