Samsung patents curved transistor shapes for stacked memory chips
Samsung has filed a patent for a semiconductor design where the active parts of a transistor have curved side surfaces rather than flat ones. This structure is intended for memory chips where transistors are stacked vertically to save space.
In the filing’s own words
A semiconductor device includes an active pattern extending in a first horizontal direction and having at least one concave portion, the active pattern including a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions, in which the at least one concave portion is defined along a side surface of the channel region and the first and second source/drain regions centered on the channel region, a bit line extending in a vertical direction and contacting the first source/drain region of the active pattern, and a gate electrode overlapping at least a portion of the channel region of the active pattern in the vertical direction and extending in a second horizontal direction, intersecting the first horizontal direction.
What exactly they claim (claim 1)
1. A semiconductor device comprising: transistors stacked in a vertical direction; a bit line electrically connected to a first side of each of the transistors; and a data storage structure electrically connected to a second side of each of the transistors, wherein the each of the transistors includes: an active pattern including a first source/drain region, a channel region, and a second source/drain region arranged sequentially in a first horizontal direction, the first horizontal direction being perpendicular to the vertical direction and a direction from the bit line toward the data storage structure; a gate electrode vertically overlapping the channel region; and a gate dielectric layer disposed between the gate electrode and the channel region, wherein at least a portion of a side surface of each of the first source/drain region, the channel region, and the second source/drain region is curved, a thickness of the channel region in the vertical direction is smaller than a thickness of the first source/drain region in the vertical direction, and a thickness of the first source/drain region in the vertical direction is smaller than a thickness of the second source/drain in the vertical direction.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE COMPRISING AN ACTIVE PATTERN HAVING A CURVED SHAPE
- Publication number
- US20260304739A1
- Application number
- 19577792
- Filed
- Mar 25, 2026
- Published
- Oct 1, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10B 12/30 Electricity & electronicsH10B 12/05 Electricity & electronicsH10D 62/235 Electricity & electronicsH10D 64/517 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.