Samsung patents stacked memory design with vertical bit lines
Samsung describes a semiconductor layout where two separate active patterns are stacked vertically. A bit line connects to the top of the second pattern, while a charge storage element touches its bottom, with gate electrodes positioned above and below the stack.
In the filing’s own words
A semiconductor device includes a first active pattern extending in a first horizontal direction, a first gate electrode at least partially overlapping the first active pattern in a vertical direction, a second active pattern including a first surface and a second surface, spaced apart from the first surface in the first horizontal direction, a bit line contacting the first surface of the second active pattern and extending in the vertical direction, a charge storage element contacting the second surface of the second active pattern, and a second gate electrode at least partially overlapping the second active pattern in the vertical direction. The first gate electrode and the second gate electrode are spaced apart from one another in the vertical direction, with the first active pattern and the second active pattern interposed therebetween.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a first active pattern extending on a substrate in a first horizontal direction; a first gate electrode at least partially overlapping the first active pattern in a vertical direction and adjacent to the first active pattern; a second active pattern extending in the first horizontal direction, wherein the second active pattern includes a first surface and a second surface, spaced apart from the first surface in the first horizontal direction; a bit line contacting the first surface of the second active pattern and extending in the vertical direction; a charge storage element contacting the second surface of the second active pattern; and a second gate electrode at least partially overlapping the second active pattern in the vertical direction and adjacent to the second active pattern, wherein the first gate electrode and the second gate electrode are spaced apart from one another in the vertical direction, with the first active pattern and the second active pattern interposed therebetween.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODES AND ACTIVE PATTERNS
- Publication number
- US20260304734A1
- Application number
- 19568060
- Filed
- Mar 16, 2026
- Published
- Oct 1, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10B 12/00 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.