/Patent Tracker
SamsungPatent applicationChips & hardwareInterest 3/10

Samsung patents circuit to smooth out clock signals in chips

Patent drawing
Patent drawing from the official filing.

Samsung describes a phase-locked loop, a common electronic circuit used to synchronize timing signals in chips. The design includes a specific component that limits how much the signal can fluctuate, helping to keep the clock steady.

Why it mattersThis is a routine improvement to chip design that helps ensure digital components operate reliably without timing errors.

In the filing’s own words

A phase locked loop is provided. The phase locked loop includes: a digitally controlled oscillator configured to generate an output clock according to a frequency control signal; a frequency divider circuit configured to generate a feedback clock by frequency dividing the output clock based on a first divide ratio value; a phase detection circuit configured to generate a phase difference signal according to a phase difference between the feedback clock and an externally provided reference clock; a loop filter circuit configured to generate a frequency control raw signal based on the phase difference signal; and a peaking suppression circuit configured to generate the frequency control signal by limiting a fluctuation range of the frequency control raw signal.

What exactly they claim (claim 1)

1. A phase locked loop, comprising: a digitally controlled oscillator configured to generate an output clock according to a frequency control signal; a frequency divider circuit configured to generate a feedback clock by frequency dividing the output clock based on a first divide ratio value; a phase detection circuit configured to generate a phase difference signal according to a phase difference between the feedback clock and an externally provided reference clock; a loop filter circuit configured to generate a frequency control raw signal based on the phase difference signal; and a peaking suppression circuit configured to generate the frequency control signal by limiting a fluctuation range of the frequency control raw signal.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
PHASE LOCKED LOOP AND OPERATION METHOD THEREOF
Publication number
US20260303104A1
Application number
19351947
Filed
Oct 7, 2025
Published
Oct 1, 2026
Inventors
5
Claims
20

Classified under

H03L 7/113 Electricity & electronicsH03L 7/093 Electricity & electronicsH03L 7/099 Electricity & electronicsH03L 7/18 Electricity & electronics

More from Samsung in Chips & hardware

Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.