Samsung patents memory chip that checks its own timing during testing
Samsung has filed a patent for a memory device that includes a built-in self-test tool. This tool checks for timing delays, known as clock skew, in the data input and output paths while the chip is still on the manufacturing wafer. It then adjusts these delays to ensure the memory operates correctly before the chip is cut and packaged.
In the filing’s own words
A memory device includes an input/output (IO) module including a write clock path and a read clock path and an IO built-in self-test (IO BIST) device. The IO BIST device is configured to, in a wafer-level test of the memory device, monitor a clock skew of each of the write clock path and the read clock path and calibrate a corresponding clock skew based on a monitoring result.
What exactly they claim (claim 1)
1. A memory device comprising: a memory cell array; an input/output (IO) module including a write clock path and a read clock path; and an IO built-in self-test (BIST) (IO BIST) device, wherein the IO BIST device is configured to, in a wafer-level test of the memory device, monitor a clock skew of each of the write clock path and the read clock path and calibrate a corresponding clock skew, based on a monitoring result.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- MEMORY DEVICE, MEMORY DEVICE INCLUDING MEMORY DIE STACK, AND WAFER-LEVEL TESTING METHOD FOR SEMICONDUCTOR CHIP
- Publication number
- US20260301833A1
- Application number
- 19413244
- Filed
- Dec 9, 2025
- Published
- Oct 1, 2026
- Inventors
- 7
- Claims
- 20
Classified under
G11C 29/023 Physics & computingG11C 29/006 Physics & computingG11C 29/022 Physics & computingG11C 29/028 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.