Samsung patents memory layout with transistors in multiple rows
Samsung describes a design for row decoders, which are parts of memory chips that tell the chip which data to read or write. The filing details arranging transistors in multiple parallel rows to generate signals for adjacent memory lines.
In the filing’s own words
A row decoder includes a first driving circuit including a first transistor among a first row of transistors, the first driving circuit being configured to generate a first driving signal onto a first wordline extending in a first direction, a second driving circuit including a second transistor among a second row of transistors, the second driving circuit being configured to generate a second driving signal onto a second wordline, the second wordline extending in the first direction and being adjacent to the first wordline in a second direction, the first transistor and the second transistor functionally corresponding to each other, and the first row of transistors and the second row of transistors extend in the second direction and being arranged along the first direction.
What exactly they claim (claim 1)
1 - 20. (canceled)
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- ROW DECODERS HAVING TRANSISTORS PLACED IN A PLURALITY OF ROWS AND MEMORY DEVICES INCLUDING THE SAME
- Publication number
- US20260301795A1
- Application number
- 19691834
- Filed
- May 29, 2026
- Published
- Oct 1, 2026
- Inventors
- 5
- Claims
- 21
Classified under
G11C 11/4087 Physics & computingG11C 11/4085 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.
