Samsung patents chip layout that squeezes more power into less space
Samsung has filed a patent for a new way to arrange transistors on a computer chip. The design uses a taller cell structure that fits between standard sizes, allowing components to connect directly without wasted filler space.
In the filing’s own words
A semiconductor cell architecture is disclosed including a merged-height cell, also known as a hyper or booster cell, having a cell height (CH) approximately one-and-one-half times that of a base unit cell (1.5×CH). The base unit cell follows a P/N/P/N vertical placement, while the merged-height cell follows a P/N/N/P configuration. The merged-height cell is vertically offset by about one-quarter cell height (0.25×CH) such that the nanosheet centers of NFET and PFET active regions in the merged-height cell align with those in the base unit cell. This alignment allows direct abutment between base and merged-height cells without dummy filler regions, maintaining process limits on active-region jogs. The 1.5×CH architecture increases effective channel width (Weff) and drivability with reduced area penalty compared to conventional 2×CH merged-height cells. The merged-height cell architecture enables merged-height standard-cell libraries for sub-3 nm nodes, improving performance, area efficiency, and routing compatibility in advanced integrated-circuit design.
What exactly they claim (claim 1)
1. A semiconductor architecture comprising: a first cell including vertically stacked active regions of alternating conductivity type; and a second cell having an intermediate height greater than a height of the first cell and less than about two times the height of the first cell, the second cell including vertically stacked active regions of alternating conductivity type, wherein the second cell is positioned to be a threshold distance from the first cell, such that a nanosheet center of a transistor-device active region in the second cell aligns with a nanosheet center in the first cell.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- MERGED-HEIGHT CELL SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING SAME
- Publication number
- US20260300603A1
- Application number
- 19448731
- Filed
- Jan 14, 2026
- Published
- Oct 1, 2026
- Inventors
- 7
- Claims
- 20
Classified under
G06F 30/392 Physics & computingH10D 30/43 Electricity & electronicsH10D 62/126 Electricity & electronicsH10D 84/8311 Electricity & electronicsH10D 84/833 Electricity & electronicsH10D 89/10 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.