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Google patents chip design that runs two AI tasks at once

Patent drawing
Patent drawing from the official filing.

Google describes a hardware design for a machine-learning chip that splits its processing power into two separate groups, or clusters. This allows the chip to run two different AI tasks at the same time by using a central controller to manage how work is distributed between the groups.

Why it mattersThis design could help devices handle multiple AI features simultaneously, such as voice recognition and image processing, without slowing down.

In the filing’s own words

Methods and systems, including computer-readable media, are described for implementing a multi-cluster architecture for a hardware machine-learning (ML) accelerator. The architecture is implemented as a hardware integrated circuit and includes a controller that communicates with one or more cores and a first and second cluster of compute tiles. Each of the first and second cluster of compute tiles is configured to execute a respective ML workload. A first workload can be assigned to the first cluster of compute tiles and a second, different workload can be assigned to the second cluster of compute tiles. The first and second workloads are executed concurrently using the first and second clusters based on a program context of at least one core that is coupled to compute tiles of the first and second cluster.

What exactly they claim (claim 1)

1. An integrated circuit comprising: a controller configured to communicate with one or more cores; a first cluster comprising a first plurality of compute tiles, the first cluster being configured to execute a first workload using the first plurality of compute tiles; and a second cluster comprising a second plurality of compute tiles, the second cluster being configured to execute a second workload using the second plurality of compute tiles; wherein the first workload and the second workload are executed concurrently based on a program context of at least one core that is instantiated by the controller and that is coupled to the first and second plurality of compute tiles.

Facts

Company
Google (Google LLC)
Official title
MULTI-CLUSTER ARCHITECTURE FOR A HARDWARE INTEGRATED CIRCUIT
Publication number
US20260299961A1
Application number
19476064
Filed
Apr 17, 2024
Published
Oct 1, 2026
Inventors
7
Claims
21

Classified under

G06F 9/3891 Physics & computingG06F 9/4818 Physics & computing
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.