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Microsoft patents chip design that guesses code paths faster

Patent drawing
Patent drawing from the official filing.

Microsoft describes a computer chip design that uses two separate counters to look ahead at software instructions. This setup allows the processor to fill its memory buffers with predicted next steps before the main instruction stream reaches them.

Why it mattersThis is a technical improvement to how processors manage their internal memory, which could lead to slightly faster computer performance.

In the filing’s own words

Branch target buffer structures are provided. A device can include a hierarchy of branch target buffers storing entries corresponding to branch instructions, the hierarchy of branch target buffers including respective branch target buffers that have progressively slower access times. The device can include a first program counter configured to generate a first program counter value associated with a next instruction of an executing application. The device can include a second program counter configured to predict a second program counter value that is associated with a subsequent instruction of the executing application that is after the next instruction. The device can include first branch prediction circuitry configured to populate a branch target buffer of the branch target buffers based on the second program counter value.

What exactly they claim (claim 1)

1. A device comprising: a hierarchy of branch target buffers storing entries corresponding to branch instructions, the hierarchy of branch target buffers including respective branch target buffers that have progressively slower access times; a first program counter configured to generate a first program counter value associated with a next instruction of an executing application; a first return stack buffer populated in accord with the first program counter value; a second program counter configured to predict a second program counter value that is associated with a subsequent instruction of the executing application that is after the next instruction; a second return stack buffer populated in accord with the second program counter value; and first branch prediction circuitry configured to populate a branch target buffer of the branch target buffers based on the second program counter value.

Facts

Company
Microsoft (Microsoft Technology Licensing, LLC)
Official title
BRANCH TARGET BUFFER RUN-AHEAD
Publication number
US20260299957A1
Application number
19706292
Filed
Jun 12, 2026
Published
Oct 1, 2026
Inventors
4
Claims
20

Classified under

G06F 9/3806 Physics & computingG06F 9/3808 Physics & computingG06F 9/3844 Physics & computing
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.