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Microsoft patents chip testing method using JTAG for design verification

Patent drawing
Patent drawing from the official filing.

Microsoft describes a method for testing chips by creating a database of internal settings and converting test instructions into JTAG commands. These commands are then sent to the chip to check if its various parts work as intended.

Why it mattersThis is a routine engineering process that helps manufacturers ensure their computer chips are built correctly before they are sold.

In the filing’s own words

The described technology provides a method including generating a register database, wherein the register database is configured to store one or more parameters of a plurality of registers, the plurality of registers representing the registers for a plurality of functional components on a system on chip (SoC), receiving a design verification flow for verifying one or more of the plurality of functional components on the SOC, generating a design verification script based on design verification flow, converting the design verification script into a series of JTAG transactions, and executing the series of JTAG transactions using a JTAG transactor.

What exactly they claim (claim 1)

1. A method, comprising: generating a register database, wherein the register database is configured to store one or more parameters of a plurality of registers, the plurality of registers representing the registers for a plurality of functional components on a system on chip (SoC); receiving a design verification flow for verifying one or more of the plurality of functional components on the SOC; generating a design verification script based on design verification flow; converting the design verification script into a series of JTAG transactions; and executing the series of JTAG transactions using a JTAG transactor.

Facts

Company
Microsoft (Microsoft Technology Licensing, LLC)
Official title
JTAG-BASED SOC DESIGN VERIFICATION ON EMULATION
Publication number
US20260299020A1
Application number
19091061
Filed
Mar 26, 2025
Published
Oct 1, 2026
Inventors
5
Claims
20

Classified under

G01R 31/31704 Physics & computingG01R 31/318307 Physics & computingG01R 31/318533 Physics & computing

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.