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Samsung patents memory chip design with stacked gates and new circuit layout

Samsung describes a semiconductor memory device where the storage cells use stacked gate electrodes to save space. The surrounding control circuits use a specific layout with isolated areas and a structure that passes through a barrier to connect components.

Why it mattersThis filing focuses on the physical arrangement of components inside a memory chip, which is a standard part of improving how computer storage is built.

In the filing’s own words

A semiconductor memory device includes a cell area and a peripheral circuit area disposed on the cell area. The cell area includes a stack structure including gate electrodes stacked in a first direction, and a channel structure disposed in the stack structure and extending in the first direction. The peripheral circuit area includes a well structure including a first surface and a second surface facing each other, the well structure including a first well area and a second well area disposed on the first surface, a first transistor being disposed in the first well area, and a second transistor being disposed in the second well area, an isolation structure that isolates the first well area and the second well area from each other, a stopper structure disposed on the isolation structure, and a through-structure that partially extends into the stopper structure in the first direction.

What exactly they claim (claim 1)

1. A semiconductor memory device comprising: a cell area; and a peripheral circuit area disposed on the cell area, wherein the cell area includes: a stack structure including a plurality of gate electrodes stacked in a first direction; and a channel structure disposed in the stack structure and extending in the first direction, and wherein the peripheral circuit area includes: a well structure including a first surface and a second surface facing each other, wherein the well structure includes a first well area and a second well area disposed on the first surface, wherein a first transistor is disposed in the first well area, and a second transistor is disposed in the second well area; an isolation structure that isolates the first well area and the second well area from each other; a stopper structure disposed on the isolation structure; and a through-structure that at least partially extends into the stopper structure in the first direction.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
Publication number
US20260293778A1
Application number
19566289
Filed
Mar 13, 2026
Published
Sep 24, 2026
Inventors
6
Claims
20

Classified under

H10W 90/297 Electricity & electronicsG11C 16/0483 Physics & computingH10B 41/10 Electricity & electronicsH10B 41/27 Electricity & electronicsH10B 41/35 Electricity & electronicsH10B 43/10 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.