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Samsung patents chip design with protective sidewall for wiring layers

Samsung describes a semiconductor chip design that adds a protective sidewall around the edges of the chip's wiring structure. This sidewall covers the outer 'dummy' areas of the wiring and aligns flush with the side of the chip substrate to protect the internal connections.

Why it mattersThis is a routine manufacturing improvement that helps protect delicate wiring during the chip packaging process, potentially increasing the durability of standard computer components.

In the filing’s own words

A semiconductor chip includes a chip substrate including a first side and a second side opposing the first side in a vertical direction, a chip wiring structure positioned on the first side of the chip substrate and including a wiring area and dummy areas surrounding the wiring area, and a protective sidewall overlapping the dummy areas of the chip wiring structure in the vertical direction and being in contact with a side surface of the chip substrate and having an inner side surface coplanar with the side surface of the chip substrate, in which the chip wiring structure includes wiring patterns positioned in the wiring area and electrically connected to the chip substrate, and a wiring insulating layer positioned in the wiring areas and the dummy areas and surrounding the wiring patterns, and the wiring insulating layer of the chip wiring structure extends to an outside of the protective sidewall.

What exactly they claim (claim 1)

1. A semiconductor chip comprising: a chip substrate comprising a first side and a second side opposing the first side in a vertical direction; a chip wiring structure positioned on the first side of the chip substrate and comprising a wiring area and dummy areas surrounding the wiring area; and a protective sidewall overlapping the dummy areas of the chip wiring structure in the vertical direction, being in contact with a side surface of the chip substrate and having an inner side surface coplanar with the side surface of the chip substrate, wherein the chip wiring structure comprises wiring patterns positioned in the wiring area and electrically connected to the chip substrate, and a wiring insulating layer positioned in the wiring area and the dummy areas and surrounding the wiring patterns, and the wiring insulating layer of the chip wiring structure extends to an outside of the protective sidewall.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
SEMICONDUCTOR CHIP, AND SEMICONDUCTOR WAFER AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Publication number
US20260293754A1
Application number
19567715
Filed
Mar 16, 2026
Published
Sep 24, 2026
Inventors
4
Claims
20

Classified under

H10W 74/141 Electricity & electronicsH10W 70/635 Electricity & electronicsH10W 74/43 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.