Samsung patents chip package with uneven pillars to improve heat flow
Samsung describes a method for building a semiconductor package where chips are mounted on a base and covered by a sealing material. The top surfaces of the chips feature small pillar structures of different widths, which are exposed through the seal to manage heat or connection points.
In the filing’s own words
A semiconductor package includes a package substrate, an interposer mounted on the package substrate via first conductive bumps; first and second semiconductor devices on the interposer and spaced apart from each other, mounted on the interposer via second conductive bumps and having concavo-convex patterns respectively formed in upper surfaces thereof; and a sealing member on the interposer covering the first and second semiconductor devices and exposing the concavo-convex patterns. The concavo-convex pattern of the first semiconductor device includes a plurality of first pillar structures provided in the upper surface of a first region of the first semiconductor device and having a first width, and a plurality of second pillar structures provided in the upper surface of a second region of the first semiconductor device and having a second width greater than the first width.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor package, comprising: providing an interposer; mounting a first semiconductor device on the interposer via first conductive bumps, the first semiconductor device including a first region and a second region; mounting at least one second semiconductor device on the interposer via second conductive bumps to be spaced apart from the first semiconductor device; forming a sealing member covering the first semiconductor device and the at least one second semiconductor device on the interposer and exposing upper surfaces of the first semiconductor device and the at least one second semiconductor device; forming a plurality of first pillar structures in an upper surface of the first region of the first semiconductor device, the plurality of first pillar structures having a first width; forming a plurality of second pillar structures in an upper surface of the second region of the first semiconductor device, the plurality of second pillar structures having a second width greater than the first width; and forming a plurality of third pillar structures in an upper surface of the at least one second semiconductor device.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
- Publication number
- US20260293733A1
- Application number
- 19694381
- Filed
- Jun 1, 2026
- Published
- Sep 24, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10W 70/685 Electricity & electronicsH10W 40/226 Electricity & electronicsH10W 40/25 Electricity & electronicsH10W 72/90 Electricity & electronicsH10W 74/127 Electricity & electronicsH10W 90/00 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.