Samsung patents stacked chip design with back-to-back passive surfaces
Samsung describes a semiconductor package where two units of chips are stacked vertically on a base. Each unit places a chip above and below a central interposer, with the inactive backs of the top and bottom chips facing each other in the middle of the stack.
In the filing’s own words
A semiconductor package including: a substrate; a first unit structure and a second unit structure on the substrate; a molding layer covering the first and second unit structures; and a conductive via within the molding layer and electrically connected to the substrate, wherein each of the first and second unit structures includes: an interposer layer; a lower unit chip; an upper unit chip; a lower redistribution layer; an upper redistribution layer, wherein each of the lower and upper unit chips has an active surface facing the interposer layer and a passive surface opposite to its active surface, and wherein the passive surface of the upper unit chip of the first unit structure and the passive surface of the lower unit chip of the second unit structure face each other.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a substrate; a first unit structure and a second unit structure sequentially stacked on the substrate; a molding layer on the substrate and covering the first unit structure and the second unit structure; and a conductive via within the molding layer and electrically connected to the substrate, wherein each of the first unit structure and the second unit structure comprises: an interposer layer; a lower unit chip below the interposer layer; an upper unit chip above the interposer layer; a lower redistribution layer between the lower unit chip and the interposer layer and electrically connected to the interposer layer, the lower unit chip, and the conductive via; an upper redistribution layer between the upper unit chip and the interposer layer and electrically connected to the interposer layer, the upper unit chip and the conductive via, wherein each of the lower unit chip and the upper unit chip has an active surface facing the interposer layer and a passive surface opposite to its active surface, and wherein the passive surface of the upper unit chip of the first unit structure and the passive surface of the lower unit chip of the second unit structure face each other.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
- Publication number
- US20260293713A1
- Application number
- 19171565
- Filed
- Apr 7, 2025
- Published
- Sep 24, 2026
- Inventors
- 1
- Claims
- 20
Classified under
H10W 70/611 Electricity & electronicsH10W 70/614 Electricity & electronicsH10W 70/65 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 90/401 Electricity & electronicsH10W 72/877 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.