Samsung patents chip layering method to strengthen narrow gaps
Samsung describes a method for building semiconductor devices by filling gaps between parallel metal lines with two different types of insulating material. The filing specifies using a softer material at the bottom and a harder material on top to maintain structural integrity in very narrow spaces.
In the filing’s own words
Disclosed is a semiconductor device including a substrate, conductive structures on the substrate and extending in parallel to each other in a first direction, and a first interlayer dielectric layer in first and second trenches between the conductive structures. A width in a second direction of the first trench may be less than a width in the second direction of the second trench. The first interlayer dielectric layer may include a lower interlayer dielectric layer and an upper interlayer dielectric layer on the lower interlayer dielectric layer, sequentially stacked. A mechanical strength of the upper interlayer dielectric layer may be greater than a mechanical strength of the lower interlayer dielectric layer.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor device comprising: forming a plurality of conductive structures on a substrate, the conductive structures extending in parallel to each other in a first direction; and forming a first interlayer dielectric layer in a first trench and a second trench, the first trench and the second trench being between the conductive structures, wherein a width in a second direction of the first trench is less than a width in the second direction of the second trench, wherein forming the first interlayer dielectric layer comprises: forming a lower interlayer dielectric layer in the first trench and the second trench; and forming an upper interlayer dielectric layer on the lower interlayer dielectric layer, wherein a mechanical strength of the upper interlayer dielectric layer is greater than a mechanical strength of the lower interlayer dielectric layer, and wherein a top surface of the upper interlayer dielectric layer in the first trench is at a level substantially same as a level of a top surface of the upper interlayer dielectric layer in the second trench.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
- Publication number
- US20260293654A1
- Application number
- 19685217
- Filed
- May 22, 2026
- Published
- Sep 24, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10W 20/435 Electricity & electronicsH10W 20/063 Electricity & electronicsH10W 20/072 Electricity & electronicsH10W 20/098 Electricity & electronicsH10W 20/42 Electricity & electronicsH10W 20/46 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.