Samsung patents stacked chip layers with vertical electrical connections
Samsung describes a chip design where two layers of semiconductor material are stacked vertically on a base. Electrical wires on the top and bottom of this stack are connected through the upper layer, allowing signals to pass between the front and back of the component.
In the filing’s own words
An integrated circuit device may include a substrate and a cell structure on an upper surface of the substrate. The cell structure may comprise a first epitaxial layer on the upper surface of the substrate, a second epitaxial layer stacked on the first epitaxial layer in a first direction that is perpendicular to the upper surface of the substrate, a front-side conductive track on an upper portion of the cell structure, and a back-side conductive track on a lower portion of the cell structure opposite to the upper portion of the cell structure in the first direction. The first epitaxial layer and the second epitaxial layer may be between the front-side conductive track and the back-side conductive track in the first direction. The back-side conductive track may be electrically connected to the front-side conductive track through the second epitaxial layer.
What exactly they claim (claim 1)
1. An integrated circuit device comprising: a substrate; and a cell structure on an upper surface of the substrate, wherein the cell structure comprises: a first epitaxial layer on the upper surface of the substrate; a second epitaxial layer stacked on the first epitaxial layer in a first direction that is perpendicular to the upper surface of the substrate; a front-side conductive track on an upper portion of the cell structure; and a back-side conductive track on a lower portion of the cell structure opposite to the upper portion of the cell structure in the first direction, wherein the first epitaxial layer and the second epitaxial layer are between the front-side conductive track and the back-side conductive track in the first direction, and wherein the back-side conductive track is electrically connected to the front-side conductive track through the second epitaxial layer.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- INTEGRATED CIRCUIT DEVICES INCLUDING STACKED TRANSISTORS WITH THROUGH-EPI CONNECTIVITY
- Publication number
- US20260293649A1
- Application number
- 19333520
- Filed
- Sep 19, 2025
- Published
- Sep 24, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10W 20/435 Electricity & electronicsH10D 84/83125 Electricity & electronicsH10D 89/10 Electricity & electronicsH10W 20/427 Electricity & electronicsH10W 20/43 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.