Samsung patents chip layout that routes power from the back of the silicon
Samsung describes a method for designing semiconductor chips where power connections are routed through the back of the silicon wafer. The design places specific power tap cells in rows that use vertical connections to link a power network on the back side to power rails on the front side.
In the filing’s own words
A method of manufacturing a semiconductor device includes designing a layout of the semiconductor device based on a circuit design, and manufacturing the semiconductor device based on the designed layout, the designing of the layout including placing a first power rail and a second power rail that extend in a first direction and are spaced apart from each other, placing a power tap cell continuously in a first row, a second row adjacent to the first row, and a third row adjacent to the second row, and placing a power delivery network on the second side of the substrate, the power tap cell including a first power through via that penetrates the substrate and extends from the power delivery network to the first power rail, and a second power through via that penetrates the substrate and extends from the power delivery network to the second power rail.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor device, comprising: designing a layout of the semiconductor device based on a circuit design; and manufacturing the semiconductor device based on the designed layout, wherein the designing of the layout comprises: placing a first power rail and a second power rail that extend in a first direction and are spaced apart from each other in a second direction, on a first side of a substrate comprising the first side and a second side that are opposite to each other; placing a power tap cell continuously in a first row, a second row adjacent to the first row, and a third row adjacent to the second row, on the first side of the substrate; and placing a power delivery network on the second side of the substrate, wherein the power tap cell comprises a first power through via that penetrates the substrate and extends from the power delivery network to the first power rail, and a second power through via that penetrates the substrate and extends from the power delivery network to the second power rail.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260293645A1
- Application number
- 19694677
- Filed
- Jun 1, 2026
- Published
- Sep 24, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10W 20/427 Electricity & electronicsG06F 30/31 Physics & computingH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 84/85 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.